View IRM7001_418306.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IRM7001
SIR Modulator/Demodulator
Dimensions in inches (mm)
A .393 (10.0) .386 (9.8) 16 1 9 B .157 (4.0) .244 (6.2) 8 .150 (3.8) .229 (5.8)
SOIC Package
.050 (1.27) BSC .068 (1.75) .054 (1.35) T .019 (.49) .014 (.35) .009 (.25) .004 (0.1)
R x 45 .009 (.25) .008 (.19) .049 (1.25) 7 .016 (.40)
FEATURES * Compliant with IrDA 1.0 Physical Layer Specifications * Interfaces with IrDA 1.0 Compliant IR Transceivers * Used in conjunction with Standard 16550 UART * Transmits/Receives either 1.6s or 3/16 Pulse Mode * Internal or External Clock Mode * Programmable Baud Rate * 2.7-5.5 V Operation * 16 Pin SOIC Package APPLICATIONS * Interfaces with IR Transceivers in: - Computer Applications: PDAs Dongle or other RS232 Adapter - Telecom Application: Modems Fax Machines Pagers - Handheld Data Collection: Industrial Medical Transportation DESCRIPTION The IRM7001 SIR-Encoder/Decoder is a CMOS modulator/ demodulator chip that is used to both encode and decode information as per the IrDA(R) SIR (Serial InfraRed) signal modulation and demodulation scheme. This chip is designed to work with Infineon IrDA compatible transceivers and all other IrDA compatible transceivers. The chip contains a clock divider circuit used to generate the 16X clock internally. This makes it very suitable for microcontroller-based embedded system design.
Notes: 1. Dimensions A and B are datums and T is a datum surface. 2. Dimensioning and tolerancing per ansi Y14.5M, 1982 3. Controlling dimension: millimeter. 4. Dimension A and B do not include mold protrusion. 5. Maximum mold protrusion 0.15 (0.005) per side.
Figure 1. IRM7001 pin out
IRM - 7001
16XCLK TXD RCV A0 A1 A2 CLK_SEL GND 1 2 3 4 5 6 7 8 16 15 14 13 12 1 11 10 9 VCC OSCIN OSCOUT PWR DN PLS MOD IR_TXD IR_RCV NRST
Figure 2. IRM7001 Block Diagram
TXD
SIR ENCODE
IR_TXD
/NRST RCV SIR DECODE IR_RCV
INT_CLOCK A0 A1 A2 16XCLK PULSEMOD CLK_SEL
CLOCK DIVIDE
Document Number: 82576 Revision 17-August-01
www.vishay.com
1
Figure 3. IRM7001 Usage Scenario (with Internal Clock)
IRM7001 IRMS/T6118 IRM5000 11 10 RxD OSCIN OSCOUT IR_TXD TXD 3 4 IO 1 5 6 IO 2 IO 3 3.6864MHz 15 14 2 TxD
Figure 4. IRM7001 Usage Scenario (with External Clock)
IRMS/T6118 IRM5000 IRM7001 2 TxD 11 10 RxD IR_RCV RCV 16XCLK CLK_SEL IR_TXD TXD 3 1 VCC BAUDOUT SOUT Microprocessor/ Controller
Microprocessor/ Controller SOUT
SIN
IR_RCV RCV A0 A1 CLK_SEL A2
SIN
Table 1. Selection of Internal Clock Rate from Crystal Oscillator
Selected Clock Rate (bps) 115200 57600 19200 9600 38400 4800 2400 TEST PURPOSE 0=L, 1=H A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CRYSTAL FREQ. DIVISION Divided by 2 Divided by 4 Divided by 12 Divided by 24 Divided by 6 Divided by 48 Divided by 96 No Division
Figure 5. Transceivers IRMS/T6118 and IRM5000 IRMS/T6118
IRM5000
IRM7001 SIR Modulator/Demodulator functions extremely well with Infineon IRMS6118/IRMT6118 and IRM5000 SIR (115 Kb/ s) Infrared Data transceivers. These products provide the user with a low component count and cost effective way of implementing an IrDA port on their products where the microcontroller does not have a built-in IrDA port support
Figures 12, 13, and 14 show the schematic, PCB front side and back side for an IRM5000/7001 based port. Table 7 provides the Bill of Materials list to implement the port. Figures 15, 16, and 17 show the schematic, PCB front and the back side for an IRMS6118/IRM7001 based port. Table 8 provides the Bill of Materials list to implement the port.
Document Number: 82576 Revision 17-August-01
www.vishay.com
2
Table 2. Pin Out and Signal Description
Signal 16X CLK Pin 1 Type DIGIN Description Positive edge triggered input clock signal that is set to 16 times the data transmission baudrate. This clock is used to drive the Encoder/Decoder state machine. Depending on the application, the 16XCLK can be provided by the application circuitry, or the internal clock divider circuitry can be used. Selection of operating mode (Internal or External clock) is selected by the CLK_SEL line. If External clock mode is selected, the application circuitry need not provide an oscillator. Negative edge triggered input signal that is normally tied to the SOUT signal of a UART (serial data to be transmitted). Data is modulated and output as IR_TXD. Output signal normally tied to SIN signal of a UART (received serial data). RCV is the demodulated output of IR_RCV. Clock multiplex signals. These signals are asserted to select the appropriate clock rate to support the following baudrate: 115200, 57600, 38400, 19200, 9600, 4800 and 2400 bps. Active high signal, used to activate either the Internal or External clock. A high on this line activates the External clock (16XCLK), or if it is pulled low, the Internal clock is used. Chip ground DIGIN Active low signal used to reset the IrDA-SIR Decode state machine. Normally this line is tied to the POR (power on reset) line of the circuit or simply to Vcc. In addition to resetting the circuitry, this signal can be asserted to disable any data reception. Input is from the SIR optoelectronics. Input signal is a 3/16th pulse which is demodulated (pulse stretched) to generate the RCV (3) output signal. This signal is the modulated TXD signal. A level high on this input puts the chip into the monoshot transmit mode. In this mode, when there is a negative transition on the TXD input, a rising edge on the internal transmit modulation state machine will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a 3.6864MHz crystal, this corresponds to 1.63us. This mode cannot be used in conjunction with the 16XCLK clock. It is meant to be used with the external crystal clock. By default, this input pin is pulled to GND. A high on this input puts the internal oscillator in POWERDOWN MODE. The internal oscillator normally is not powered down.
TXD RCV A0-A2 CLK_SEL GND NRST
2 3 4-6 7 8 9
DIGIN DIGOUT DIGIN DIGIN
IR_RCV IR_TXD PULSEMOD
10 11 12
DIGIN DIGOUT DIGIN (with pulldown)
POWER-DN
13
DIGIN (with pulldown)
OSCOUT OSCIN VCC Function
14 15 16
ANAOUT ANAIN
Crystal Oscillator input Crystal Oscillator input Power (see Electrical Specifications for detail)
The IRM7001 can be used in conjunction with a microcontroller/microprocessor that has a serial communication interface (UART). Prior to communication the processor selects the transmission baudrate by selecting appropriate levels on the A0-A2 lines. This process sets up the communication system to operate at the prescribed data rate. After this initial step, serial data can be transmitted or received at the prescribed data rate. The IRM7001 consists of two state machines-the SIR Encode and SIR Decode blocks, and a sequential block Clock Divide, which synthesizes the required internal signal INT-CLOCK, based on the inputs A0-A2 and the CLK_ SEL line. The IRM7001 can be placed into Internal Clock Mode (CLK_SEL set to low) or External Clock Mode (CLK_ SEL set to high). The internal clock signal INT_CLOCK source is then gated appropriately through to the INT_CLOCK signal. In application where the external 16XCLK signal is provided, there is no need to provide an oscillator.
The SIR Encode block is driven by TXD (negative edge triggered signal), which initiates the modulation state machine, resulting in the modulated IR_TXD signal (which drives the SIR compatible electronics). The SIR Decode block is driven by the IR_RCV signal (negative edge triggered signal, derived from the optoelectronics). IR_RCV is demodulated by the SIR Decode block resulting in the RCV signal, which represents the stretched input pulse. In addition, there is a pin provided to the user, called the PULSEMOD. A high level input on this pin activates the 1.6us mode on the IR_TXD. In this mode, whenever there is a negative edge on the TXD, the rising edge on the modulation state machine will set the IR_TXD signal high for 6 crystal clock cycles no matter what the selection on A2, A1 and A0 lines is. With a crystal frequency of 3.6864MHz, this corresponds to a high pulse of 1.63us.
Document Number: 82576 Revision 17-August-01
www.vishay.com
3
ELECTRICAL SPECIFICATIONS Table 3. Absolute Maximum Ratings
Parameter Power Supply Voltage Input/Output Voltage Power Dissipation Output Current Operating Temperature Storage Temperature Symbol VCC VI/VO Pmax IO TA TS -100 -40 -65 Min. -0.5 -0.5 Max. +7.0 VCC +0.5 0.46 100 +85 +150 Unit V V W mA C C
Table 4. AC Characteristics VCC=5 V 10%, TA=-20 to +85C
Parameter Propagation Delay Time Output Rise Time Output Fall Time Output Capacitance Symbol tpd tr tf COUT Conditions VCC=5.5 V, CL=50 pF VCC=5.5 V, CL=50 pF VCC=2.7 V, CL=50 pF VCC=5.5 V, CL=50 pF VCC=2.7 V, CL=50 pF 4.0 10 4.0 11 7.0 16 8.0 16 Min. Typ. Max. 80 12 24 11 26 50 Unit ns ns ns ns ns
PF
Operating conditions Operating conditions are specified with respect to GND unless otherwise specified. All the parameters below have been specified for VCC in the range of 2.7 V(min) and 5.5 V(max) and for a temperature range of -20C to 85C. Propagation Delay Time in the output buffer is the time taken from the input passing VCC/2 to the time of the output reaching VCC/2 with 50pF as the output load. The output rise time is the time taken for the output (RCV, IRTXD) to rise from 10% to 90% of final value. The output fall time is the time taken for the outputs (RCV, IR_TXD) to fall from 90% of original value to 10% of final value.
Document Number: 82576 Revision 17-August-01
www.vishay.com
4
Table 5. Operating Conditions at VCC=2.7 V
Parameter Supply voltage Input voltage Ambient temperature High-Level Input Voltage Low-Level Input Voltage Output High Voltage Output Low Voltage Static Power Dissipation Dynamic Power Dissipation Static Current Consumption Dynamic Power Dissipation Max Clk Frequency(16XCLK) Minimum Pulse Width(IR_TXD) Pulse Width on monoshot (IR_TXD) Output Capacitance on Output Pads used for simulation Value of pulldown resistor used on POWERDN & PULSEMOD input pins Trigger Low Level Input Voltage (For /NRST input pin) Trigger High Level Input Voltage (For /NRST input pin) Symbol VCC VIN Ta VIH VIL VOH VOL PSTAT PDYN ISTAT IDYN f16xclk tmpw tmpw COUT RDWN VIL_TRIG VIH_TRIG 114 0.7 1.7 152 0.8 1.85 1630 1630 1710 1730 50 256 0.9 1.9 0.11 5.4 40 2 Min 2.7 0 -20 0.7 VCC 0 2.2 0.5 0.15 8.1 54 3 2 Typ 5 Max 5.5 VCC +85 VCC 0.3 VCC Unit V V C V V V V mW mW A mA MHz ns ns pF KOhms V V IOH=2.0 mA IOL=2.0 mA Conditions
Document Number: 82576 Revision 17-August-01
www.vishay.com
5
Table 6. Operating Conditions at VCC=5.5 V
Parameter Supply voltage Input voltage Ambient temperature High-Level Input Voltage Low-Level Input Voltage Output High Voltage Output Low Voltage Static Power Dissipation Dynamic Power Dissipation Static Current Consumption Dynamic Power Dissipation Max Clk Frequency(16XCLK) Minimum Pulse Width(IR_TXD) Pulse Width on monoshot (IR_TXD) Output Capacitance on Output Pads used for simulation Value of pulldown resistor used on POWERDN & PULSEMOD input pins Trigger Low Level Input Voltage (For /NRST input pin) Trigger High Level Input Voltage (For /NRST input pin) Symbol VCC VIN Ta VIH VIL VOH VOL PSTAT PDYN ISTAT IDYN f16xclk tmpw tmpw COUT RDWN VIL_TRIG VIH_TRIG 114 0.7 1.7 152 0.8 1.85 1630 1630 1710 1730 50 256 0.9 1.9 0.44 11 80 2 Min 2.7 0 -20 0.7 VCC 0 4.5 0.5 0.61 16.5 110 3 2 Typ 5 Max 5.5 VCC +85 VCC 0.3 VCC Unit V V C V V V V mW mW A mA MHz ns ns pF KOhms V V IOH=2.0 mA IOL=2.0 mA Conditions
IRDA Parameters 1. The Max Clk Frequency (f16xClk) represents the maximum clock frequency that the IRM7001 internal state machine should be driven at. Under normal circumstances, this clock input should not exceed 16*115200(bps) =1.8432 MHz. This is the maximum transmission rate under the IRDA Physical layer 1.0 specification. The IRM7001 can handle higher clock rates, but the recommended maximum is as specified above. 2. The Minimum Pulse Width (tmpw), represents the minimum pulse width of the encoded IR_TXD pulse as well as the minimum pulse width for the IR_RCV pulse. As per the IRDA specification, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3*(1/1.8432 MHz) = 1.63 S. The minimum pulse width that can be handled by the IRM7001 is 250ns, which is within the IRDA SIR specifications. Under normal circumstances using a 16XCLK clock that does not exceed 2 MHz, the minimum pulse width of IR_TXD should not be shorter than 1.63 s.
Document Number: 82576 Revision 17-August-01
www.vishay.com
6
IRDA-SIR Encoding and Decoding Scheme Overview of Encoding Scheme Figures 5 and 6 outline the IRDA-SIR encoding scheme. The encoding scheme relies on a clock being present, which is set to 16 times the data transmission baud rate (16XCLK). The encoder sends a pulse for every space (0) that is sent. On a high to low transition of the TXD line, the generation of the pulse is delayed for 7 clock cycles of the 16XCLK clock before the pulse is set high for 3 clock cycles (or 3/16 of a bit time) and subsequently pulled low. This in essence generates a 3/16th bit time pulse centered around the bit of information (0) that is being transmitted. For consecutive spaces, pulses with a 1 bit time delay are generated in series. If a logic 1 (mark) is sent, then the encoder does not generate a pulse.
Figure 6. Encoding Scheme--Macro Perspective
16 Cycles 16 Cycles 16 Cycles 16 Cycles
16 XCLK TXD 7 CS IRTXD 3 CS
Figure 7. IrDA-SIR Encoding Scheme--Detailed Timing Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16XCLK
TXD
IRTXD
Overview of the Decoding Scheme The IRDA-SIR decoding modulation method can be thought of as a pulse stretching scheme: Every high to low transition of the IR-RXD line signifies the arrival of a 3/16th pulse. This pulse needs to be stretched to accommodate 1 bit time (or 16 16XCLK cycles). Every pulse that is received is translated into a'O' or space on the RXD line. If a series of pulses separated by 1 bit time are received, then the net result is a I bit time low pulse for every 3/16th pulse received (see figure 9). To be correctly received and interpreted by a UART, the stretched pulse must be at least 3/4 of a bit time in duration.
Figure 8. Decoding Scheme--Macro Perspective
16 Cycles 16 Cycles 16 Cycles 16 Cycles
16 XCLK IRRXD RXD 3 CS
Figure 9. IrDA-SIR Decoding Scheme--Detailed Timing Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16XCLK
IRRXD
RXD
16 Clock Cycles = 1 Bit Time
Document Number: 82576 Revision 17-August-01
www.vishay.com
7
Figure 10. Monoshot Operation
12345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CRYSTAL CLK
INT CLK (DIVBY2)
TXD
INTERNAL IRTXD OUTPUT 6 CRYSTAL CYCLES IRTXD (MONOSHOT)
Fig 7 illustrates the operation of the monoshot when the internal clock is set to divide by 2 mode, i.e. when A2=0, A1=0 and A0=0. A rising edge on the internal modulation state machine (here called IRTXD OUTPUT), will cause the output on the IRTXD to go up for 6 crystal clock cycles. With a 3.6864MHz Figure 11. IRM5000/7001 Schematic with External Clock
5.2
clock, this corresponds to a pulse of 1.63us. The duration of this pulse is independent of the code A2, A1, A0 and is always 6 clock cycles of the crystal, corresponding to the monoshot operation.
1 - LED Anode 2 - Vcc C2 22F C1 0.1F
5V Power Supply
C3 R1 0.1F 10K
9 /NRST SOUT 3-Tx 2 TxD
16 Vcc IR_TxD 11 2
15 LED Vcc ANODE
TxD
UART 16550
BAUDOUT SIN 4-Tx 3 7
IRM7001
16XCLK RCV CLK_SEL IR_RCV GND 8 10 3
IRM5000
RxD
SD GND 4 6
12-GND
Document Number: 82576 Revision 17-August-01
www.vishay.com
8
Figure 12. IRM5000/7001 Schematic using Internal Clock
VCC RLED Watt
1/ 4 1/ 4
2.7 V 5.0 V
0 5.1
W W
RLED
1 - LED Anode 2 - Vcc 11-PLSMD C2 22F R1 10K 13 2 4 5 6 9 12 16 Vcc 11 2 1 5 Vcc LED ANODE TxD C1 0.1F
Power Supply
O5 O6
C3 0.1F
9-POWERDWN 4 - Tx 5 - A0 8 - A1 7 - A2 6 - Rx 10-CLK_SEL 3-16XCLK 15 R2 10M
/NRST PLSMD 9-POWERDWN TxD A0 A1
P/ Controller
SOUT IO1 IO2 IO3 SIN O4
IR_TxD
A2 3 RCV 7 CLK_SEL 1 16XCLK
IRM7001
IR_RCV 10 3
IRM5000
RxD SD GND 6
Data Rate A2 A1 A0 115.2K 0 00 57.6K 0 01 19.2K 0 10 9.6K 0 11 38.4K 1 00 4.8K 1 01 2.4K 1 10
OSCIN OCSOUT GND XTL 8 14 3.6864MHz 15pF
4
C5 12- GND
15pF C4
Table 7. IRM5000/7001 Eval Board Bill of Materials Component Case type Description IRM7001-Encoder/ Decoder IC (Infineon) IRMS5000-IR Data Transceiver (Infineon) HC49 1206 1206 1210 C 1210 1206 1206 3.6864MHz Crystal Oscillator 10K Resistor 10M Resistor 0.1F Capacitor 22F Capacitor 0.1F Capacitor 15pF Capacitor 15pF Capacitor DO2436-2 (Infineon) Quantity
Figure 13. IRM5000/7001 Eval Board Looking from Front Side
U1
1 EA
U2
1 EA
Y1 R1 R2 C1 C2 C3 C4 C5 PCB
1 EA 1 EA 1 EA 1 EA 1 EA 1 EA 1 EA 1 EA 1 EA Figure 14. IRM5000/7001 Eval Board Looking from Back Side
Document Number: 82576 Revision 17-August-01
www.vishay.com
9
Figure 15. IRMS6118/7001 Schematic using Internal Clock
VCC RLED Watt
1/ 4 1/ 4
2.7 V 5.0 V
0 6.8
W W
RLED
1 - LED Anode
2 - Vcc
Power Supply
SOUT 3 - Tx 5 - A0 6 - A1 7 - A2 4 - Rx
C3 0.1F
R1 10K 12 9 /NRST PLSMD 2 4 A0 5 6 3 A1 A2 RCV OSCIN TxD
C2 22F
C1 0.1F
16 Vcc 11 3 TxD
6
1
Vcc LED ANODE
IR_TxD
P / Controller
IO1 IO2 IO3 SIN
IRM7001
IR_RCV 10 4
IRMS6118
RxD SD GND 8
15 Data Rate A2 A1 115.2K 00 57.6K 00 19.2K 01 9.6K 01 38.4K 10 4.8K 10 2.4K 11 A0 0 1 0 1 0 1 0 3.6864MHz 10M R2 15pF C5
OCSOUT GND CLK-SEL XTL 14 8 7
5
C4 8 - GND
15pF
Table 8. IRMS6118/7001 Eval Board Bill of Materials Component Case type Description IRM7001-Encoder/ Decoder IC (Infineon) IRMS6118-IR Data Transceiver (Infineon) HC49 1206 1206 1210 C 1210 1206 1206 3.6864MHz Crystal Oscillator 10K Resistor 10M Resistor 0.1F Capacitor 22F Capacitor 0.1F Capacitor 15pF Capacitor 15pF Capacitor DO2436-(Infineon) Quantity
Figure 16. IRMS6118/7001 Eval Board Looking from Front Side
U1
1 EA
U2
1 EA
Y1 R1 R2 C1 C2 C3 C4 C5 PCB
1 EA 1 EA 1 EA 1 EA 1 EA 1 EA 1 EA 1 EA 1 EA
Note: For proper operation Pin 7 of IRM7001 should be connected to GND.
Figure 17. IRMS6118/7001 Eval Board Looking from Back Side
Document Number: 82576 Revision 17-August-01
www.vishay.com
10
Design Notes: 1. When internal is used, CLK_SEL should be held low (connected to GND). In case of external clock CLK_SEL should be tied high (VCC). 2. If PULSEMOD is held high and the internal clock is used, the IR_TXD is limited to a duration of 1.6s irrespective of data rate. This helps in reducing LED current at lower data rates. This function cannot be used with external clock (16XCLK). 3. There are two methods of putting the internal oscillator cell in POWERDN MODE. Firstly, whenever CLKSEL line is asserted high, the oscillator cell is automatically put in power down mode. Secondly, the user may also decide to put the oscillator in power down mode by providing a high signal on the POWERDN input pin. Normally the POWERDN pin stays low.
PACKAGING Production Package The package is SOIC 16 pins (150 mils) plastic package. Chips will be available in Tape and Reel (2500 units per reel). QUALITY AND RELIABILITY E.S.D. and latch-up Maximum DC current through any pin thus avoiding latch-up: +/- 100 mA Electrostatic discharge protection: 4000 V for mono-supply voltage Electrostatic discharge protection: 2000 V for multi-supplies voltages E.S.D. sensitivity: MIL STD-8833015.7 Class 2 Specific requirements: environmental endurance A. Permanence of marking: MIL-STD-883 - Method 2015 B. Solderability: MIL-STD-883 - Method 2003 C. Resistance to soldering heat: MIL-STD-883 - Method 200
Document Number: 82576 Revision 17-August-01
www.vishay.com
11

▲Up To Search▲

Price & Availability of IRM7001

	To Download IRM7001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .